The present invention relates to input/output (I/O) interfaces and more particularly to sharing resources between input and output functions.
Due to rapid progress in design techniques and process technology, the speed of integrated circuit (IC) devices has increased considerably. Such a rapid change in the speed of IC devices has also led to increasingly demanding requirements on the memory devices that interface with these IC's. Besides having a high storage capacity, modern memory chips must be able to interface with other chips at increasingly faster speeds. Consequently, the use of Double Data-Rate (DDR) and Quadruple Data-Rate (QDR) memory devices, or more generally a multiple data-rate interface, has become increasingly common. A DDR interface is a synchronous (that is, clocked) interface where data is transferred on each edge of a clock signal. Specifically, alternating data bits in a DDR signal are transferred on the rising and falling edges of a clock signal, thereby doubling the peak throughput of the memory device without increasing the system clock frequency. Similar steps and results exist for Low Voltage Differential Signaling (LVDS).
In order to transmit these higher data-rate signals, additional circuitry is needed as compared to the circuitry needed for single data-rate (SDR) I/O. Additional circuitry may also be needed to ensure accurate data transfers during SDR I/O with increased clock frequency or during multiple data-rate I/O.
Also, to provide varying data transfer rates, an I/O element typically has sufficient circuitry dedicated to input and sufficient circuitry dedicated to output. Unfortunately, this capability adds more circuit elements and wires, and thus more area and cost.
Thus, what are needed are circuits, methods, and apparatus for providing the flexibility of multiple I/O configurations including multiple data-rate options while using a minimal amount of additional area and cost.